Recently, designers of ASICs (Application Specific Integrated Circuits) have expressed interest in incorporating DRAM macros to enhance on-chip storage density. Greater processing widths and speed available now to ASICs is beginning to demand storage densities which stretch the limits of static random access memory (SRAM), which has traditionally been embedded in those ASICs which include a processor element such as a microprocessor.
Owing to their diverse circuit implementations and design goals, production verification testing of ASICs and DRAMs has differed widely. Traditional ASICs, having mainly logic circuits such as for a microprocessor and SRAM elements, are production tested in only a few minutes, because failures are manifested by relatively large defect currents (from several to several hundred microamps (>1×10E-6), which are manifested either before or after very short durations of high stress testing. On the other hand, it may take tens of hours of burn-in testing to manifest all early life failures within a DRAM because of much smaller tolerances for defect currents, which typically measure in sub-picoamps (<1×10E-12). Moreover, since DRAMs typically have greater integration density than logic circuits, the defect density is greater. As illustrated in FIG. 1, it has been noted that the defect density (the number of defects within a given volume) in an integrated circuit lies in inverse relation to the cube of the size of the defective element. For example, assuming an element size in a DRAM which is one half the element size used in a microprocessor, the defect density of the DRAM is expected to be more than eight times the defect density of the microprocessor.
Thus, when a DRAM macro is embedded into an ASIC, a problem is presented for production verifying the completed integrated circuit. If traditional ASIC test methods are used which are short in duration but at high stress, many marginal DRAM memory elements will not be identified at time of test. Instead, such marginal DRAM elements will only fail later once the ASIC is packaged and used in the final product by the end user. However, if traditional DRAM test methods are used which have long duration, this poses a major disruption to standard ASIC test and reliability screening processes.
Table 1 below indicates failure modes for elements within a DRAM, and the frequencies with which they are manifested through burn-in testing of each integrated circuit.
TABLE 1Array FailureFrequencyRoot CauseNo. of Lost BitsSingle cell failure 98%Crystal defect1Oxide defectPaired cell failure 1%Contact defect2Wordline × Bitline <1%Contact-WL short>2Partial bitline or <1%Open metal>2Partial wordlinefailureFull bitline or<<1%miscellaneous256 to 4096 bitsFull wordline failure
It is apparent from the above and Table 1 that ASICs which incorporate a DRAM will perform poorly unless provision is made for the DRAM early life failures. From Table 1, it is apparent that the majority of early life failures affects a single bit memory cell. However, a significant amount of early life failures affect multiple memory cells such as partial or full bitline or wordline failures. Since currently practiced long duration DRAM testing is undesirable with present ASICs testing, an alternative approach is needed for handling DRAM early life failures while meeting reliability goals in the final product.
FIG. 2 is a block diagram illustrating the structure and operation of a conventional DRAM, and is provided and described here as background to the present invention. A DRAM may be “standalone”, i.e. the only circuitry on an integrated circuit, or it may be “embedded”, i.e. incorporated as a memory along with a logic core or microprocessor on integrated circuits such as ASICs. As shown in FIG. 2, a DRAM typically includes a number of banks, shown here as Bank<0:3>. Each bank contains an array of DRAM memory cells 201, each memory cell which lies at the intersection between a wordline 203 and a bitline 205. By way of example, read access to a memory cell 201 is performed in the following manner. Address (ADDR), and commands for bank select, row command (Row Cmd) and column command (Col Cmd) are presented to a row control unit (Row Cntl 207) and column control unit (Col Cntl 209). From these signals, row decoder (Row Dec. 211) selects and activates a wordline 203. The activated wordline 203 causes information stored in all memory cells coupled to that wordline 203 to be placed on respective bitlines, including the information from memory cell 201 which is placed on bitline 205. The retrieved information from the memory cells are then transferred to sense amplifiers 213, but in typical DRAMs only a fraction, e.g. one fourth, of the bits accessed by the wordline 203 are selected and output onto a databus DQ 217 by column decoders 215, column selection being based on the column address portion of the address ADDR.